1

Rev. 00C

09/12/05

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

• Industrial temperature available

• Lead-free available

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 128K words by 32 bits, 128K words by 36 bits,

and 256K words by 18 bits, fabricated with

CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

PRELIMINARY INFORMATION

SEPTEMBER 2005

FAST ACCESS TIME

Symbol

Parameter

-250

-200

Units

Clock Access Time

2.6

3.1

ns

Cycle Time

4

5

ns

Frequency

250

200

MHz