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IS61NLP12836A-250B3I Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS61NLP12836A-250B3I Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
9 / 29 page Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. 00C 09/12/05 ISSI® IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP 256K x 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb NC VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection VDD +3.3V/2.5V Power Supply VSS Ground for output Buffer VDDQ Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable |
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