Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. A

03/17/06

IS65C256AL

IS62C256AL

-25 ns

-45 ns

Symbol

Parameter

Min.

Max.

Min. Max.

Unit

Write Cycle Time

25

—

45

—

ns

CE to Write End

15

—

35

—

ns

Address Setup Time to Write End

15

—

25

—

ns

Address Hold from Write End

0

—

0

—

ns

Address Setup Time

0

—

0

—

ns

WE Pulse Width

15

—

25

—

ns

Data Setup to Write End

12

—

20

—

ns

Data Hold from Write End

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the write.

4. Tested with

OE HIGH.

AC WAVEFORMS

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE

WE

CS_WR1.eps