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74F174 Datasheet(PDF) 5 Page - NXP Semiconductors |
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74F174 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 8 page Philips Semiconductors Product specification 74F174 Hex D flip-flop October 7, 1988 5 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VM SF00166 CP Qn VM tw(H) tPHL VM tPLH 1/fMAX tw(L) VM Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM SF00158 MR Qn VM tw(L) tPHL VM tREC CP VM Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock recovery Time th(H) ts(H) CP SF00191 VM VM VM VM VM VM th(L) ts(L) Dn Waveform 3. Data Setup and Hold Times TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) 0V 0V tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T. PULSE GENERATOR RL CL RT VIN VOUT Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM SF00006 |
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