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IS61VPS25618A-200B3 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS61VPS25618A-200B3 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 26 page Integrated Silicon Solution, Inc. — 1-800-379-4774 1 Rev. 00A 10/07/04 ISSI® Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5% • JEDEC 100-Pin TQFP, 119-ball PBGA, and 165-ball PBGA packages • Automotive temperature available • Lead Free available DESCRIPTION The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and network- ing applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 bits. The IS61(64)LPS/VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/ VPS25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single mono- lithic circuit. All synchronous inputs pass through regis- ters controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable ( BWE) input combined with one or more individual byte write signals ( BWx). In addition, Global Write ( GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM PRELIMINARY INFORMATION FEBRUARY 2005 FAST ACCESS TIME Symbol Parameter 250 200 Units tKQ Clock Access Time 2.6 3.1 ns tKC Cycle Time 4 5 ns Frequency 250 200 MHz |
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