10

Rev. B

02/24/05

IS62WV51216ALL, IS62WV51216BLL

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the

CS1 , CS2 and WE inputs and at

least one of the

LB and UB inputs being in the LOW state.

2. WRITE = (

CS1) [ (LB) = (UB) ] (WE).

AC WAVEFORMS

DATA-IN VALID

DATA UNDEFINED

HIGH-Z

ADDRESS

CS1

CS2

WE

DOUT

DIN

LB, UB

45ns

55 ns

70 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

45

—

55

—

70

—

ns

35

—

45

—

60

—

ns

Address Setup Time to Write End

35

—

45

—

60

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

35

—

45

—

60

—

ns

WE Pulse Width

35

—

40

—

50

—

ns

Data Setup to Write End

20

—

25

—

30

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

WE LOW to High-Z Output

—

20

—

20

—

30

ns

WE HIGH to Low-Z Output

5

—

5

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to

2. The internal write time is defined by the overlap of

CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the

write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

OE is LOW.