Electronic Components Datasheet Search |
|
N74F1763N Datasheet(PDF) 8 Page - NXP Semiconductors |
|
N74F1763N Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 16 page Philips Semiconductors Product specification 74F1763 Intelligent DRAM controller (IDC) 1999 Jan 08 8 AC ELECTRICAL CHARACTERISTICS (Continued) LIMITS NO PARAMETER TEST CONDITIONS TA = 25_C VCC = +5.0V "10% CL = 300pF RL = 70W TA = 0_C TO +70_C VCC = +5.0V "10% CL = 300pF RL = 70 W UNIT MIN TYP MAX MIN MAX 30 Propagation delay REQ( #) to DTACK( ") 6 8 11.5 6 12 ns 31 Propagation delay CP( ") to DTACK( #) 7.5 9.5 12 7.5 13 ns 32 Propagation delay REQ( ") to DTACK (3-state) 9 12 13 9 15.5 ns 33 MA0–9 (refresh address) to RAS( #) skew 1/2tcp – 5 1/2tcp – 6.5 ns 34 RAS( #) to MA0–9 (refresh address) skew 1tcp – 2 1tcp – 2.5 ns 35 RAS( ") to RAS(#) skew (precharge) PRECHRG = 0 4tcp – 6 4tcp – 3.5 4tcp – 1.5 4tcp – 6.5 4tcp – 6.5 ns 36 RAS( ") to RAS(#) skew (precharge) PRECHRG = 1 3tcp – 6 3tcp – 3.5 3tcp – 1.5 3tcp + 1 3tcp – 6.5 ns NOTES: 1. REQ High hold means that, if REQ is High at the rising clock edge, it is guaranteed that the REQ input was not sampled as Low. 2. A 50% duty cycle clock is recommended. If the duty cycle of the clock is not 50%, REQ should be held high for enough time such that a falling CP clock edge samples REQ as High. This is to ensure that refresh cycles don’t get locked-up. 3. When ALE is Low, the address input latches are in the transparent mode and therefore any changes in the address inputs will be propagated to the MA0–9 outputs. Figure 2 illustrates RA0–9 inputs propagating to the MA0–9 outputs, but later in the cycle, if ALE is still Low when the CA0–9 inputs are multiplexed to the MA0–9 outputs the CA0–9 inputs will be in the transparent mode. 4. If PAGE is High and REQ is Low, RAS is automatically negated after approximately 4 CP clock cycles. If PAGE is Low and REQ is also Low, RAS will be negated when PAGE goes High. RAS will always be negated when REQ goes High regardless of the state of PAGE input. TIMING DIAGRAMS SF01403 1 2 CP 3 4 5 RCP 6 Figure 1. Clock cycle timing |
Similar Part No. - N74F1763N |
|
Similar Description - N74F1763N |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |