8

Programmable Microelectronics Corp.

Issue Date: December, 2003, Rev: 1.3

PMC

Pm25LV512/010

t

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Table 4. Read Status Register Bit Definition

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-

tion for the Pm25LV010. The Pm25LV010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all

of the memory blocks can be protected (locked out) from write. The Pm25LV512 is divided into 2 blocks where all

of the memory blocks can be protected (locked out) from write. Any of the locked-out blocks will therefore be READ

only. The locked-out block and the corresponding status register control bits are shown in Table 5.

The three bits, BP0, BP1, and WPEN, are nonvolatile cells that have the same properties and functions as the

regular memory cells (e.g., WREN, RDSR).

WRITE ENABLE (WREN): The device will power up in the write disable state when Vcc is applied. All write

instructions must therefore be preceded by the WREN instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write

commands. The WRDI instruction is independent of the status of the WP# pin.

READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/

BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write

Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction.

During internal write cycles, all other commands will be ignored except the RDSR instruction.

7

t

i

B6

t

i

B5

t

i

B4

t

i

B3

t

i

B2

t

i

B1

t

i

B0

t

i

B

N

E

P

W

XXX

1

P

B0

P

BN

E

WY

D

R

Table 3. Status Register Format