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74F50109 Datasheet(PDF) 5 Page - NXP Semiconductors |
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74F50109 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 12 page Philips Semiconductors Product specification 74F50109 Synchronizing dual J–K positive edge-triggered flip-flop with metastable immune characteristics September 14, 1990 5 MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’ 78910 1012 1011 1010 109 108 107 106 1014 1015 = fCfI t’ in nanoseconds MTBF in seconds one year 106 108 1010 1012 one week 10,000 years 100 years SF00589 NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 108 sec Figure 4. TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES Tamb = 0°C Tamb = 25°C Tamb = 70°C VCC τ T0 τ T0 τ T0 5.5V 125ps 1.0 X 109 sec 138ps 5.4 X 106 sec 160ps 1.7 X 105 sec 5.0V 115ps 1.3 X 1010 sec 135ps 9.8 X 106 sec 167ps 3.9 X 104 sec 4.5V 115ps 3.4 X 1013 sec 132ps 5.1 X 108 sec 175ps 7.3 X 104 sec FUNCTION TABLE INPUTS OUTPUTS OPERATING SD RD CP J K Q Q MODE L H X X X H L Asynchronous set H L X X X L H Asynchronous reset L L X X X H H Undetermined* H H ↑ X X q q Hold H H ↑ h l q q Toggle H H ↑ h h H L Load ”1” (set) H H ↑ l l L H Load ”0” (reset) H H ↑ l h q q Hold ’no change” NOTES: H = High–voltage level h = High–voltage level one setup time prior to low–to–high clock transition L = Low–voltage level l = Low–voltage level one setup time prior to low–to–high clock transition q = Lower case indicate the state of the referenced output prior to the low–to–high clock transition X = Don’t care ↑ = Low–to–high clock transition ↑ = Not low–to–high clock transition * = Both outputs will be high if both SD and RD go low simultaneously |
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