Philips Semiconductors

Product specification

74F50728

Synchronizing cascaded dual positive

edge-triggered D-type flip-flop

September 14, 1990

5

FUNCTION TABLE

INTERNAL

OUTPUTS

INPUTS

REGISTER

OUTPUTS

OPERATING MODE

SDn

RDn

CPn

Dn

Q

Qn

Qn

L

H

X

X

H

H

L

Asynchronous set

H

L

X

X

L

L

H

Asynchronous reset

L

L

X

X

X

H

H

Undetermined*

H

H

↑

h

h

H

L

Load ”1”

H

H

↑

l

l

L

H

Load ”0”

H

H

L

X

NC

NC

NC

Hold

NOTES:

H = High voltage level

h

= High voltage level one setup time prior to low–to–high

clock transition

L

= Low voltage level

l

= Low voltage level one setup time prior to low–to–high

clock transition

NC= No change from the previous setup

X = Don’t care

*

= This setup is unstable and will change when either set of

reset return to the high–level

↑ = Low–to–high clock transition.

** = Data entering the flip–flop requires two clock cycles to

arrive at the output (see logic diagram)

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the

operating free air temperature range.)

SYMBOL

PARAMETER

RATING

UNIT

Supply voltage

–0.5 to +7.0

V

Input voltage

–0.5 to +7.0

V

Input current

–30 to +5

mA

Voltage applied to output in high output state

V

Current applied to output in low output state

40

mA

Operating free air temperature range

Commercial range

0 to +70

Industrial range

–40 to +85

Storage temperature range

–65 to +150

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

MIN

NOM

MAX

UNIT

Supply voltage

4.5

5.0

5.5

V

High–level input voltage

2.4

V

Low–level input voltage

0.8

V

Input clamp current

–18

mA

High–level output current

–3

mA

Low–level output current

20

mA

Operating free air temperature range

Commercial range

0

+70

Industrial range

–40

+85