Philips Semiconductors

Product specification

74F5074

Synchronizing dual D-type flip-flop/clock driver

September 14, 1990

5

MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’

78910

t’ in nanoseconds

MTBF in seconds

one year

one week

10,000 years

100 years

SF00589

Figure 4.

TYPICAL VALUES FOR

τ

τ

τ

5.5V

125ps

138ps

160ps

5.0V

115ps

135ps

167ps

4.5V

115ps

132ps

175ps

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING

SD

RD

CP

D

Q

Q

MODE

L

H

X

X

H

L

Asynchronous set

H

L

X

X

L

H

Asynchronous reset

L

L

X

X

H

H

Undetermined*

H

H

↑

h

H

L

Load “1”

H

H

↑

l

L

H

Load “0”

H

H

↑

X

NC

NC

Hold

NOTES:

H =

High voltage level

h

=

High voltage level one setup time prior to low–to–high clock transition

L

=

Low voltage level

l

=

Low voltage level one setup time prior to low–to–high clock transition

NC=

No change from the previous setup

X =

Don’t care

↑ =

Low–to–high clock transition

↑ =

Not low–to–high clock transition

*

=

This setup is unstable and will change when either set or reset return to the high level