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EVAL-ADV7321EB Datasheet(PDF) 9 Page - Analog Devices |
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EVAL-ADV7321EB Datasheet(HTML) 9 Page - Analog Devices |
9 / 88 page ADV7320/ADV7321 Rev. 0 | Page 9 of 88 TIMING DIAGRAMS t9 t11 CLKIN_A C9–C0 t10 t12 CONTROL INPUTS Y0 Y1 Y2 Y3 Y4 Y5 Y9–Y0 t14 CONTROL OUTPUTS t13 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME P_HSYNC, P_VSYNC, P_BLANK Cr4 Cb4 Cr2 Cb2 Cr0 Cb0 Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001) t9 t11 CLKIN_A C9–C0 t10 t12 CONTROL INPUTS Y0 Y1 Y2 Y3 Y4 Y5 Y9–Y0 t14 CONTROL OUTPUTS t13 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME S9–S0 Cr4 Cr3 Cr2 Cr1 Cr0 Cr5 Cb4 Cb3 Cb2 Cb1 Cb0 Cb5 P_HSYNC, P_VSYNC, P_BLANK Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001) |
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