8
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© 2002 QuickLogic Corporation
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QL4058 QuickRAM Data Sheet Rev H
Figure 5: Loads used for tPXZ
Table 7: I/O Cell Input Delays
Symbol
Parameter
Propagation Delays (ns)
Fanout
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and
TA = 25
°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
1
2
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
t
ISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
t
IH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
tIOCLK
Input Register Clock to Q
0.7
1.0
1.2
1.5
2.5
3.0
t
IORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
t
IESU
Input Register Clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
tIEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
Table 8: I/O Cell Output Delays
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
3
50
75
100
150
t
OUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
t
OUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
tPZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
t
PZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
t
PHZ
Output Delay High to Tri-statea
a. These loads are used for t
PXZ (see Figure 5)
2.0
-
-
-
-
tPLZ
Output Delay High to Tri-statea
1.2
-
-
-
-
1ΚΩ
1ΚΩ
tPHZ
tPLZ
5 pF
5 pF
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