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EM4022V15WS11 Datasheet(PDF) 4 Page - EM Microelectronic - MARIN SA |
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EM4022V15WS11 Datasheet(HTML) 4 Page - EM Microelectronic - MARIN SA |
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4 / 15 page  Copyright 2002, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com EM4022 Power storage capacitor calculation The global current consumption of the device defines the external storage capacitor. When the device modulate, the supply voltage is picked from the supply capacitor and should never decrease under the falling edge of the power on reset (VPONF). If this occurs, the device goes in a reset mode and any data transmission is aborted. The worst case for the storage capacitor calculation is when the device is put in the electromagnetic field. At this moment the supply reaches the VPONR and start to modulate. During modulation the power store in the capacitor must be high enough so that at the end of the modulation the supply is higher than VPORF.. This means that the voltage reduction on the capacitor must be less than the hysteresis of the power on reset (VPHYS). And this when the chip has a supply voltage of around the power on reset threshold The total current consumption from the storage capacitor is defined by the modulation current IMOD, This current is the consumption of the power on reset block, oscillator and the logic which work at a typical frequency of 125KHz. The GAP current is also included in this parameter. The duration where this currents is present for the capacitor calculation, is dependent of the data rate Calculation example : Below we define typical cases combinations : FOSC = 125 KHz VPHYS = 120 mV IMOD = 9 µA Data rate is 4 KBaud. CPx I F V BaudRate nF MOD OSC HYS = == − − ** ** ** * ** * * * . 128 10 9 10 128 10 125 10 160 10 4 10 14 4 3 63 33 3 Of course, this value can be adapted to the electromagnetic power and to the performances that must be achieved. If a tag is put in a field within a short time, the emitting power must be high enough to charge up the capacitor. The chip integrates a 140pF supply capacitor. Block Diagram Shunt PON VDD VSS GAP N P C R TST VDD VDD CG RG DG D1 D3 D2 D4 OSC CP Q1 Q2 CR M COIL1 GAP SI XCLK TMC VSS VDD COIL2 LOGIC VSS VSS VSS Fig. 5 |
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