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EDI2AG272128V9D1 Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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EDI2AG272128V9D1 Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 11 page EDI2AG272128V-D1 White Electronic Designs 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com July 1999 ADVANCED* White Electronic Designs Corp. reserves the right to change products or specifications without notice. 2 Megabyte Sync/Sync Burst, Small Outline DIMM FEATURES The EDI2AG272128VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM (144 contacts) Module, organized as 2x128Kx72. The Module contains four (4) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Sync/Sync Burst, Flow-Through, with support for linear burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, provides a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC# Low, and ADSP#/ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations. *This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear Burst Mode Clock Controlled Registered Bank Enables (E1#, E2#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Aysnchronous Output Enable (G#) Internally self-timed Write Gold Lead Finish 3.3V ± 10% Operation Access Speed(s): TKHQV=8.5, 9, 10, 12ns Common Data I/O High Capacitance (30pf) drive, at rated Access Speed Single total array Clock Multiple Vcc and Gnd |
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