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EDI2CG272128V85D1 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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EDI2CG272128V85D1 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 12 page EDI2CG272128V 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs August 2000 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifications without notice. SYNCHRONOUS BURST - TRUTH TABLE Operation E1# E2# ADSP# ADSC# ADV# GW# G# CK DQ Addr. Used Deselected Cycle, Power Down; Bank 1 H X X L X X X L-H High-Z None Deselected Cycle, Power Down; Bank 2 X H X L X X X L-H High-Z None Read Cycle, Begin Burst; Bank 1 L H L X X X L L-H Q External Read Cycle, Begin Burst; Bank 1 L H L X X X H L-H High-Z External Read Cycle, Begin Burst; Bank 2 H L L X X X L L-H Q External Read Cycle, Begin Burst; Bank 2 H L L X X X H L-H High-Z External Write Cycle, Begin Burst; Bank 1 L H H L X L X L-H D External Write Cycle, Begin Burst; Bank 2 H L H L X L X L-H D External Read Cycle, Begin Burst; Bank 1 L H H L X H L L-H Q External Read Cycle, Begin Burst; Bank 1 L H H L X H H L-H High-Z External Read Cycle, Begin Burst; Bank 2 H L H L X H L L-H Q External Read Cycle, Begin Burst; Bank 2 H L H L X H H L-H High-Z External Read Cycle, Continue Burst; Bank 1 X H X H L H L L-H Q Next Read Cycle, Continue Burst; Bank 1 X H X H L H H L-H High-Z Next Read Cycle, Continue Burst; Bank 2 H X X H L H L L-H Q Next Read Cycle, Continue Burst; Bank 2 H X X H L H H L-H High-Z Next Read Cycle, Continue Burst; Bank 1 H H X H L H L L-H Q Next Read Cycle, Continue Burst; Bank 1 H H X H L H H L-H High-Z Next Read Cycle, Continue Burst; Bank 2 H H X H L H L L-H Q Next Read Cycle, Continue Burst; Bank 2 H H X H L H H L-H High-Z Next Write Cycle, Continue Burst; Bank 1 X H H H L L X L-H D Next Write Cycle, Continue Burst; Bank 1 H H X H L L X L-H D Next Write Cycle, Continue Burst; Bank 2 H X H H L L X L-H D Next Write Cycle, Continue Burst; Bank 2 H H X H L L X L-H D Next Read Cycle, Suspend Burst; Bank 1 X H H H H H L L-H Q Current Read Cycle, Suspend Burst; Bank 1 X H H H H H H L-H High-Z Current Read Cycle, Suspend Burst; Bank 2 H X H H H H L L-H Q Current Read Cycle, Suspend Burst; Bank 2 H X H H H H H L-H High-Z Current Read Cycle, Suspend Burst; Bank 1 H H X H H H L L-H Q Current Read Cycle, Suspend Burst; Bank 1 H H X H H H H L-H High-Z Current Read Cycle, Suspend Burst; Bank 2 H H X H H H L L-H Q Current Read Cycle, Suspend Burst; Bank 2 H H X H H H H L-H High-Z Current Write Cycle, Suspend Burst; Bank 1 X H H H H L X L-H D Current Write Cycle, Suspend Burst; Bank 1 H H X H H L X L-H D Current Write Cycle, Suspend Burst; Bank 2 H X H H H L X L-H D Current Write Cycle, Suspend Burst; Bank 2 H H X H H L X L-H D Current |
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