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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

EDI2CG472128V

July 1999

Rev 1

ADVANCED

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS

DIMM Pins

Symbol

Type

Description

2, 87, 4, 89, 7, 92,

9, 94, 12, 96, 10,

93, 8, 91, 5, 88, 3

A0-A16

Input

Synchronous

Addresses: These inputs are registered and must meet the setup and hold times

around the rising edge of CK. The burst counter generates internal addresses

associated with A0 and A1, during burst and wait cycle.

107, 106, 23, 22,

109, 108, 25, 24

BW1#, BW2#,

BW3#, BW4#,

BW5#, BW6#,

BW7#, BW8#

Input

Synchronous

Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.

BW0/ controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1.

BW2# controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.

BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.

BW6# controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.

104

BWE#

Input

Synchronous

Write Enable: This active LOW input gates byte write operations and must meet the

setup and hold times around the rising edge of CK.

19

GW#

Input

Synchronous

Global Write: This active LOW input allows a full 72-bit WRITE to occur independent

of the BWE# and BWx# lines and must meet the setup and hold times around the

rising edge of CK.

101

CK

Input

Synchronous

Clock: This signal registers the addresses, data, chip enables, write control and

burst control inputs on its rising edge. All synchronous inputs must meet setup and

hold times around the clock’s rising edge.

98, 15, 99, 14

E1#, E2#,

E3#, E4#

Input

Synchronous

Bank Enables: These active LOW inputs are used to enable each individual bank

and to gate ADSP#.

103

G#

Input

Output Enable: This active LOW asynchronous input enables the data output drivers.

111

ADV#

Input

Synchronous

Address Status Processor: This active LOW input is used to control the internal burst

counter. A HIGH on this pin generates wait cycle (no address advance).

27

ADSP#

Input

Synchronous

Address Status Processor: This active LOW input, along with EL# and EH# being

LOW, causes a new external address to be registered and a READ cycle is initiated

using the new address.

26

ADSC#

Input

Synchronous

Address Status Controller: This active LOW input causes device to be de-selected or

selected along with new external address to be registered.

A READ or WRITE cycle is initiated depending upon write control inputs.

17

MODE

Input Static

Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR

BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.

36, 50,

64, 78

Input

Asynchronous

Snooze: These active HIGH inputs put the individual banks in low power

consumption standby mode. For normal operation, this input has to be either

LOW or NC (no connect).

Various

DQ0-63

Input/Output

Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is

DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is

DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.

113, 120, 127, 134,

141, 148, 155, 162

DQP0-7

Input/Output

Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.

DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity

bit for DQ-32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.

DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a

Various

Vcc

Supply

Core Power supply: +3.3V -5%/+10%

Various

Vss

Ground

Ground