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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

EDI2GG464128V

October 2004

Rev. 1

PIN DESCRIPTIONS

DIMM Pins

Symbol

Type

Description

3, 5, 7, 9, 13,

15, 17, 19, 20,

23, 18, 16, 14,

10, 8, 6

A0-A15

Input

Synchronous

Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of

38

GW#

Input

Synchronous

Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE# and BWx#

lines and must meet the setup and hold times around the rising edge of CK.

27

CK

Input

Synchronous

Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its

rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.

36, 32,

35, 31

E1#, E2#

E3#, E4#

Input

Synchronous

Bank Enables: These active LOW inputs are used to enable each individual Synchronous bank and to gate

ADSP#.

37

G#

Input

Output Enable: This active LOW asynchronous input enables the data output drivers.

Various

DQ0-63

Input/Output

Various

Vcc

Supply

Core power supply: +3.3V -5%/+10%

Various

Vss

Ground

Ground