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EDI2GG464128V12D Datasheet(PDF) 4 Page - White Electronic Designs Corporation |
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EDI2GG464128V12D Datasheet(HTML) 4 Page - White Electronic Designs Corporation |
4 / 8 page 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI2GG464128V October 2004 Rev. 1 PIN DESCRIPTIONS DIMM Pins Symbol Type Description 3, 5, 7, 9, 13, 15, 17, 19, 20, 23, 18, 16, 14, 10, 8, 6 A0-A15 Input Synchronous Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. 38 GW# Input Synchronous Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CK. 27 CK Input Synchronous Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. 36, 32, 35, 31 E1#, E2# E3#, E4# Input Synchronous Bank Enables: These active LOW inputs are used to enable each individual Synchronous bank and to gate ADSP#. 37 G# Input Output Enable: This active LOW asynchronous input enables the data output drivers. Various DQ0-63 Input/Output Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Various Vcc Supply Core power supply: +3.3V -5%/+10% Various Vss Ground Ground |
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