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EM6153V50 Datasheet(PDF) 7 Page - EM Microelectronic - MARIN SA |
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EM6153V50 Datasheet(HTML) 7 Page - EM Microelectronic - MARIN SA |
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7 / 11 page  R EM6153 Copyright © 2006, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com 06/06, rev. B, prelim. Functional Description VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level applied on the VIN input. The threshold voltage at which reset is asserted or released (VRESET) is determined by the external voltage divider between VDD and VSS, as shown on Fig. 8. A part of VDD is compared to the internal voltage reference. To determine the values of the divider, the leakage current at VIN must be taken into account as well as the current consumption of the divider itself. Low resistor values will need more current, but high resistor values will make the reset threshold less accurate at high temperature, due to a possible leakage current at the VIN input. The sum of the two resistors (R1 + R2) should stay below 500 kΩ. The formula is: VRESET = VREF x (1 + R1/R2). Example: choosing R1 = 200 kΩ and R2 = 100 kΩ gives VRESET =4.56 V (typical) for version V50 and V53. At power-up the reset output ( RES ) is held low (see Fig. 5). When VIN becomes greater than VREF, the RES output is held low for an additional power-on-reset (POR) delay TPOR (defined with the external resistor connected at ROSC pin). The TPOR delay prevents repeated toggling of RES even if VDD voltage drops out and recovers. The TPOR delay allows the microprocessor’s crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the power- down reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on VIN is typically 3 μs. Timer Programming The on-chip oscillator allows the user to adjust the power-on reset (POR) delay TPOR and the watchdog time TWD by changing the resistor value of the external resistor ROSC connected between the pin ROSC and VSS (see Fig. 8). The closed and open window times (TCW and TOW) as well as the watchdog reset pulse width (TWDR), which are TTCL dependent, will vary accordingly. The watchdog time TWD can be obtained with figures 9 to 12 or with the Excel application EM6151ResCalc.xls available on EM website. TPOR is equal to TWD with the minimum and maximum tolerances increased by 1% (For Version 53, TPOR is one fourth of TWD). Note that the current consumption increases as the frequency increases. Voltage Regulator The EM6153 has a 5 V, 150 mA, low dropout voltage regulator. The low supply current makes the EM6153 particularly suitable for automotive systems which remain continuously powered. The input voltage range is 4 V to 40 V for operation and the input protection includes both reverse battery (42 V below ground) and load dump (positive transients up to 45 V). There is no reverse current flow from the OUTPUT to the INPUT when the INPUT equals VSS. This feature is important for systems which need to implement (with capacitance) a minimum power supply hold-up time in the event of power failure. To achieve good load regulation a 10 μF capacitor (or greater) is needed on the INPUT (see Fig. 8). Tantalum or aluminum electrolytic are adequate for the 10 μF capacitor; film types will work but are relatively expensive. Many aluminum electrolytic have electrolytes that freeze at about –30°C, so tantalums are recommended for operation below –25°C. The important parameters of the 10 μF capacitor are an effective series resistance of lower than 4 Ω and a resonant frequency above 500 kHz. A 10 μF capacitor (or greater) and a 100 nF capacitor are required on the OUTPUT to prevent oscillations due to instability. The specification of this 10 μF capacitor is as per the 10 μF capacitor on the INPUT (see previous paragraph). The EM6153 will remain stable and in regulation with no external load and the dropout voltage is typically constant as the input voltage fall below its minimum level (see Table 2). These features are especially important in CMOS RAM keep-alive applications. Power Dissipation Care must be taken not to exceed the maximum junction temperature (+125°C). The power dissipation within the EM6153 is given by the formula: PTOTAL = (VINPUT – VOUTPUT) × IOUTPUT + (VINPUT) × ISS The maximum continuous power dissipation at a given temperature can be calculated using the formula: PMAX = ( 125°C – TA) / Rth(j-a) where Rth(j-a) is the thermal resistance from the junction to the ambient and is specified in Table 2. Note that Rth(j-a) given in Table 2 assumes that the package is soldered to a PCB (see figure 16). The above formula for maximum power dissipation assumes a constant load (i.e. >100 s). The transient thermal resistance for a single pulse is much lower than the continuous value. CAN-Bus Sleep Mode Detector (version 55) When the microcontroller goes into a standby mode, it implies that it does not send any pulses on the TCL input of the EM6153. After three reset pulse periods (TCW + TOW + TWDR) on the RES output, the circuit switches on an internal resistor of 1 M Ω, and it will have a reset pulse of typically 3 ms every 1 second on the RES output. When a TCL edge (rising or falling) appears on the TCL input or the power supply goes down and up, the circuit switches to the ROSC. Watchdog Timeout Period Description The watchdog timeout period is divided into two periods, a closed window period (TCW) and an open window period (TOW), see Fig. 4. If no pulse is applied on the TCL input during the open window period TOW, the RES output goes low for a time TWDR. When a pulse is applied on the TCL input, the cycle is restarted with a close window period. For example if TWD = TPOR = 100ms, TCW = 80 ms, TOW = 40ms and TWDR = 2.5ms. When VIN recovers after a drop below VREF, the pad RES is set low for the time TPOR during which any TCL activation is disabled. |
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