NX29F010
6
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signals during VCC power-up and power-down transitions, or
from system noise.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on
OE, CE, or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE = VIL,
CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while
OE is a logical one.
Power-Up Write Inhibit
If
WE = CE = VIL and OE = VIH during power-up, the device
does not accept commands on the rising edge of
WE. The
internal state machine is automatically reset to reading
array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions Table 5 defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of
WE or CE,
whichever happens later. All data is latched on the rising
edge of
WE or CE, whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
The system must issue the reset command to re-enable the
device for reading array data if the error status bit, DQ5, is set
high after an erase or program operation, or while in the
auto-select mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operation's table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Reset Command
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the device for reading array data. Once
erasure begins, however, the device ignores reset com-
mands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before program-
ming begins. This resets the device to reading array data.
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an auto-select command sequence.
Once in the auto-select mode, the reset command must be
written to return to reading array data.
If the error status bit, DQ5, goes high during a program or
erase operation, writing the reset command returns the
device to reading array data.
Auto-select Command Sequence
The auto-select command sequence allows the host sys-
tem to access the manufacturer and device equivalent
codes, and determines whether or not a sector is protected.
The Command Definitions Table 5 shows the address and
data requirements. This method is an alternative to that
shown in the Auto-select Codes (High Voltage Method)
Table 4, which is intended for PROM programmers and
requires VID on address bit A9.
The auto-select command sequence is initiated by writing
two unlock cycles, followed by the auto-select command.
The device then enters the auto-select mode, and the
system may read at any address any number of times,
without initiating another command sequence.
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