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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

EDI88130CS

March 2002

Rev. 11

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

Access Times of 15*, 17, 20, 25, 35, 45, 55ns

Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

CS1#, CS2 & OE# Functions for Bus Control

Inputs and Outputs Directly TTL Compatible

Organized as 128Kx8

Commercial, Industrial and Military Temperature

Ranges

Thru-hole and Surface Mount Packages JEDEC

Pinout

• 32 pin Sidebrazed Ceramic DIP, 400 mil

(Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil

(Package 9)

• 32 lead Ceramic SOJ (Package 140)

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

Block Diagram

Memory Array

Address

Buffer

Address

Decoder

I/O

Circuits

A0-16

I/O0-7

WE#

OE#

CS1#

CS2

FIGURE 1 – PIN CONFIGURATION

Single +5V (±10%) Supply OperationThe

EDI88130CS is a high speed, high performance,

128Kx8 bits monolithic Static RAM.

An additional chip enable line provides system memory

security during power down in non-battery backed up

systems and memory banking in high speed battery

backed systems where large multiple pages of memory

are required.

The EDI88130CS has eight bi-directional input-output lines

to provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data

retention function for battery back-up applications.

Military product is available compliant to MIL-PRF-

38535.

* 15ns access time is advanced information, contact factory for availability.

32 DIP

32 SOJ

32 CLCC

32 FLATPACK

TOP VIEW

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A15

CS2#

WE#

A13

A8

A9

A11

OE#

A10

CS1#

I/O7

I/O6

I/O5

I/O4

I/O3

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

32 QUAD LCC

TOP VIEW

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

4321

32

31

30

14

15

16

17

18

19

20

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

WE#

A13

A8

A9

A11

OE#

A10

CS1#

I/O7

PIN DESCRIPTION

I/O0-7

Data Input/Output

A0-16

Address Inputs

WE#

Write Enable

CS1#, CS2

Chip Select

OE#

Output Enable

Power Supply

Ground

NC

Not Connected