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W83176R-733 Datasheet(PDF) 9 Page - Winbond |
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W83176R-733 Datasheet(HTML) 9 Page - Winbond |
9 / 14 page DUAL BANK DDR BUFFER FOR VIA CHIPSET - 6 - W83176R-733/W83176G-733 7.8 Slew rate reference table SR<1:0> STATUS 10/01 Normal (default) 11 Strong 00 Weak 7.9 Register 20: Skew & Slew Rate Control (Default: 8Ah) BIT NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRB_TSKEW<2> 0 5 DDRB_TSKEW<1> 0 4 DDRB_TSKEW<0> 0 DDRB True clock outputs with FB_OUTB True clock SKEW control bits 3 DDRAT/C0_SR<1> 1 2 DDRAT/C0_SR<0> 0 DDRAT/C0 slew rate control bits 1 DDRAT/C1_SR<1> 1 0 DDRAT/C1_SR<0> 0 DDRAT/C1 slew rate control bits 7.10 Register 21: Slew Rate Control (Default: AAh) BIT NAME PWD DESCRIPTION 7 DDRAT/C2_SR<1> 1 6 DDRAT/C2_SR<0> 0 DDRAT/C2 slew rate control bits 5 DDRAT/C3_SR<1> 1 4 DDRAT/C3_SR<0> 0 DDRAT/C3 slew rate control bits 3 DDRAT/C4_SR<1> 1 2 DDRAT/C4_SR<0> 0 DDRAT/C4 slew rate control bits 1 DDRAT/C5_SR<1> 1 0 DDRAT/C5_SR<0> 0 DDRAT/C5 slew rate control bits 7.11 Register 22: Slew Rate Control (Default: AAh) BIT NAME PWD DESCRIPTION 7 DDRBT/C0_SR<1> 1 6 DDRBT/C0_SR<0> 0 DDRBT/C0 slew rate control bits 5 DDRBT/C1_SR<1> 1 4 DDRBT/C1_SR<0> 0 DDRBT/C1 slew rate control bits |
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