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PACKAGE DISSIPATION RATINGS

(1) (2)

ELECTRICAL CHARACTERISTICS

TPS54317

SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006

PACKAGE

THERMAL IMPEDANCE

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

JUNCTION-TO-CASE

24-Pin RHF with solder

19.7

°C/W

1.7

°C/W

(1)

Maximum power dissipation may be limited by overcurrent protection.

(2)

Test board conditions:

•

3 inch x 3 inch, 4 layers, thickness: 0.062 inch

•

2 oz. copper traces located on the top of the PCB

•

2 oz. copper ground plane on the bottom of the PCB

•

2 oz. copper ground planes on the 2 internal layers

•

6 thermal vias (see the Recommended land pattern, Figure 12)

T

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE, VIN

Input voltage range, VIN

3

6

V

6.2

9.6

Quiescent current

8.4

12.8

mA

phase pin open

Shutdown, SS/ENA = 0 V

1

1.4

UNDERVOLTAGE LOCK OUT

Start threshold voltage, UVLO

2.95

3

V

Stop threshold voltage, UVLO

2.7

2.8

Hysteresis voltage, UVLO

0.14

0.16

V

Rising and falling edge deglitch,

2.5

µs

BIAS VOLTAGE

Output voltage, VBIAS

2.7

2.8

2.9

V

100

µA

CUMULATIVE REFERENCE

Accuracy

0.882

0.891

0.900

V

REGULATION

0.04

%/V

0.09

%/A

OSCILLATOR

SYNC

≤ 0.8 V, RT open

280

350

420

Internally set free-running frequency

kHz

range

SYNC

≥ 2.5 V, RT open

440

550

660

RT = 100 k

Ω (1% resistor to AGND)

460

500

540

Externally set free-running frequency

kHz

range

RT = 43 k

Ω (1% resistor to AGND)

995

1075

1155

High-level threshold voltage, SYNC

2.5

V

Low-level threshold voltage, SYNC

0.8

V

50

ns

Frequency range, SYNC

330

1600

kHz

0.75

V

1

V

Minimum controllable on time

150

ns

Maximum duty cycle

90%

(1)

Specified by design

(2)

Static resistive loads only

(3)

Specified by the circuit used in Figure 10.

3

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