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W3E16M72SR-XBX Datasheet(PDF) 7 Page - White Electronic Designs Corporation |
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W3E16M72SR-XBX Datasheet(HTML) 7 Page - White Electronic Designs Corporation |
7 / 16 page 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E16M72SR-XBX February 2005 Rev. 2 DESELECT The DESELECT function (CS# HiGH) prevents new commands from being executed by the DDR SDRAM. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. COMMAND READ NOP NOP NOP CL = 2.5 DON'T CARE TRANSITIONING DATA DQ DQS T0 T1 T2 T2n T3 T3n COMMAND READ NOP NOP NOP CL = 2 DQ DQS CLK CLK# T0 T1 T2 T2n T3 T3n Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA CLK CLK# OUTPUT DRIVE STRENGTH The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. COMMANDS The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. FIGURE 4 – CAS LATENCY FIGURE 5 – EXTENDED MODE REGISTER DEFINITION DLL Enable Disable DLL DS A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus Operating Mode A10 A11 11 01 BA0 BA1 QFC# E0 0 1 Drive Strength Normal Reduced E1 0 1 QFC# Function Disabled Reserved E22 0 - Operating Mode Reserved Reserved E2, E1, E0 Valid - E12 0 - E10 0 - E9 0 - E8 0 - E7 0 - E6 0 - E5 0 - E4 0 - E3 0 - A12 E11 0 - 1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFE# function is not supported. |
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