W3E16M64S-266BC datasheet(1/16 Pages) WEDC

Part #	W3E16M64S-266BC

Description	16Mx64 DDR SDRAM

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

W3E16M64S-XBX

February 2005

Rev. 4

BENEFITS

50% SPACE SAVINGS

Reduced part count

Reduced I/O count

• 17% I/O Reduction

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

Upgradeable to 32M x 64 density

(W3E32M64S-XBX)

GENERAL DESCRIPTION

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,

dynamic random-access, memory using 4 chips containing

268,435,456 bits. Each chip is internally conﬁgured as a

quad-bank DRAM. Each of the chip’s 67,108,864-bit banks

is organized as 8,192 rows by 512 columns by 16 bits.

The 128 MB DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access for the 128MB DDR SDRAM effectively consists

of a single 2n-bit wide, one-clock-cycle data tansfer at the

internal DRAM core and two corresponding n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during READs

16Mx64 DDR SDRAM

FEATURES

DDR Data Rate = 200, 250, 266Mbps

Package:

• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm

2.5V ±0.2V core power supply

2.5V I/O (SSTL_2 compatible)

Differential clock inputs (CLK and CLK#)

Commands entered on each positive CLK edge

Internal pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

Programmable Burst length: 2,4 or 8

Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (one per byte)

DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

DLL to align DQ and DQS transitions with CLK

Four internal banks for concurrent operation

Two data mask (DM) pins for masking write data

Programmable IOL/IOH option

Auto precharge option

Auto Refresh and Self Refresh Modes

Commercial, Industrial and Military Temperature

Ranges

Organized as 16M x 64

Weight: W3E16M64S-XBX - 2 grams typical

* This product is subject to change without notice.

21

25

66

TSOP

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11.9

22.3

Monolithic Solution

Actual Size

W3E16M64S-XBX

S

A

V

I

N

G

S

Area

I/O

Count

4 x 265mm2 = 1060mm2

4 x 66 pins = 264 pins

525mm2

50%

219 Balls

17%

W3E16M64S-XBX

White Electronic Designs

66

TSOP

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