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W3E32M72SR-250SBM Datasheet(PDF) 9 Page - White Electronic Designs Corporation |
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W3E32M72SR-250SBM Datasheet(HTML) 9 Page - White Electronic Designs Corporation |
9 / 19 page W3E32M72SR-XSBX 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. TRUTH TABLE - COMMANDS (NOTE 1) NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” NAME (FUNCTION) CS# RAS# CAS# WE# ADDR DESELECT (NOP) (9) H X X X X NO OPERATION (NOP) (9) L H H H X ACTIVE (Select bank and activate row) ( 3) L L H H Bank/Row READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col BURST TERMINATE (8) L H H L X PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code AUTO REFRESH or SELF REFRESH (Enterselfrefreshmode) (6, 7) L L L H X LOAD MODE REGISTER (2) L L L L Op-Code TRUTH TABLE - DM OPERATION NAME (FUNCTION) DM DQs WRITE ENABLE (10) L Valid WRITE INHIBIT (10) H X 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. an AUTO REFRESH command. Each DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. SELF REFRESH* The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and REGISTER FUNCTION TABLE INPUTS OUTPUT Q RESET# RCK RCK# INPUT H ↑↓ HH H ↑↓ LL H L or H L or H X Q0 L X, or floating X, or floating X, or floating L * Self refresh available in commercial and industrial temperatures only. |
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