Electronic Components Datasheet Search |
|
W3E32M72SR-266SBI Datasheet(PDF) 10 Page - White Electronic Designs Corporation |
|
W3E32M72SR-266SBI Datasheet(HTML) 10 Page - White Electronic Designs Corporation |
10 / 19 page W3E32M72SR-XSBX 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR ABSOLUTE MAXIMUM RATINGS Parameter Unit Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V Voltage on I/O pins relative to Vss -0.5V to VCCQ +0.5V V Operating Temperature TA (Mil) -55 to +125 °C Operating Temperature TA (Ind) -40 to +85 °C Storage Temperature, Plastic -55 to +125 °C NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (NOTE 13) Parameter Symbol Max Unit Input Capacitance: CK/CK# CI1 8 pF Addresses, BA0-1 Input Capacitance CA 10 pF Input Capacitance: All other input-only pins CI2 9pF Input/Output Capacitance: I/Os CIO 10 pF BGA THERMAL RESISTANCE Description Symbol Typical Units Notes Junction to Ambient (No Airflow) Theta JA 15.8 °C/W 1 Junction to Ball Theta JB 15.7 °C/W 1 Junction to Case (Top) Theta JC 7.2 °C/W 1 Note: These typical thermal resistances are for each DRAM die; if using total power of the MCP, divide above values by five(5). Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.whiteedc. com in the application notes section for modeling conditions. SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. REGISTER RECOMMENDED OPERATING CONDITIONS Parameter/Condition Min Max Unit VIH AC high-level input voltage Data inputs VREF+310mV V VIL AC low-level input voltage Data inputs VREF-310mV V VIH High-level input voltage RESET# 1.7 V VIL Low-level input voltage RESET# 0.7 V Note: The RESET# input of the device must be held at a valid logic level (not floating) to ensure proper device operation. |
Similar Part No. - W3E32M72SR-266SBI |
|
Similar Description - W3E32M72SR-266SBI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |