W3E232M16S-XSTX

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

December 2005

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

PRELIMINARY*

BURST LENGTH

Read and write accesses to the DDR SDRAM are burst

oriented, with the burst length being programmable,

as shown in Figure 3. The burst length determines

the maximum number of column locations that can be

accessed for a given READ or WRITE command. Burst

lengths of 2, 4 or 8 locations are available for both the

sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation

or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1-Ai when the burst length is set to two; by A2-Ai when the

burst length is set to four (where Ai is the most significant

column address for a given configuration); and by A3-Ai

when the burst length is set to eight. The remaining (least

significant) address bit(s) is (are) used to select the starting

location within the block. The programmed burst length

applies to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by

the burst length, the burst type and the starting column

address, as shown in Table 1.

READ LATENCY

The READ latency is the delay, in clock cycles, between

the registration of a READ command and the availability

of the first bit of output data. The latency can be set to 2

or 2.5 clocks.

If a READ command is registered at clock edge n, and the

latency is m clocks, the data will be available by clock edge

n+m. Table 2 below indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

be brought HIGH. Following the NOP command, a

PRECHARGE ALL command should be applied. Next a

LOAD MODE REGISTER command should be issued for

the extended mode register (BA1 LOW and BA0 HIGH)

REGISTER command to the mode register (BA0/BA1

parameters. Two-hundred clock cycles are required

between the DLL reset and any READ command. A

PRECHARGE ALL command should then be applied,

placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must

MODE REGISTER command for the mode register with

the reset DLL bit deactivated (i.e., to program operating

parameters without resetting the DLL) is required.

Following these requirements, the DDR SDRAM is ready

for normal operation.

REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to define the specific mode of

operation of the DDR SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS latency,

and an operating mode, as shown in Figure 3. The Mode

Register is programmed via the MODE REGISTER SET

command (with BA0 = 0 and BA1 = 0) and will retain

the stored information until it is programmed again or

the device loses power. (Except for bit A8 which is self

clearing).

Reprogramming the mode register will not alter the contents

of the memory, provided it is performed correctly. The Mode

Register must be loaded (reloaded) when all banks are

idle and no bursts are in progress, and the controller must

wait the specified time before initiating the subsequent

operation. Violating either of these requirements will result

in unspecified operation.

Mode register bits A0-A2 specify the burst length, A3

specifies the type of burst (sequential or interleaved),

A4-A6 specify the CAS latency, and A7-A12 specify the

operating mode.