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W3E32M64S-250SBC Datasheet(PDF) 4 Page - White Electronic Designs Corporation |
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W3E32M64S-250SBC Datasheet(HTML) 4 Page - White Electronic Designs Corporation |
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4 / 17 page  4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3E32M64S-XSBX July 2006 Rev. 5 A0-12 A0-12 BA0-1 BA0-1 CLK0 CLK CAS DQ0 DQ15 CKE0 CKE CS0 CS DQML0 DQML DQMH0 DQMH RAS1 WE1 CAS1 DQ0 DQ15 WE U1 RAS A0-12 BA0-1 CLK1 CLK CAS DQ16 DQ31 RAS0 WE0 CAS0 DQ0 DQ15 WE U0 RAS CKE1 CKE CS1 CS DQML1 DQML DQMH1 DQMH RAS2 WE2 CAS2 DQ0 DQ15 WE U2 RAS A0-12 BA0-1 CLK2 CLK CAS DQ32 DQ47 CKE2 CKE CS2 CS DQML2 DQML DQMH2 DQMH RAS3 WE3 CAS3 DQ0 DQ15 WE U3 RAS A0-12 BA0-1 CLK3 CLK CAS DQ48 DQ63 CKE3 CKE CS3 CS DQSL3 DQSL DQSH3 DQSH Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= CLK3 CLK VREF DQSL2 DQSL DQSH2 DQSH VREF DQSL1 DQSL DQSH1 DQSH VREF DQSL0 DQSL DQSH0 DQSH VREF CLK2 CLK CLK1 CLK CLK0 CLK VREF DQML3 DQML DQMH3 DQMH FIGURE 2 FUNCTIONAL BLOCK DIAGRAM INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power- up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. |
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