W3E64M72S-XBX

8

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

June 2005

Rev. 0

ADVANCED

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

TABLE 1 – BURST DEFINITION

Burst

Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved

2

A0

0

0-1

0-1

1

1-0

1-0

4

A1

A0

0

0

0-1-2-3

0-1-2-3

0

1

1-2-3-0

1-0-3-2

1

0

2-3-0-1

2-3-0-1

1

1

3-0-1-2

3-2-1-0

8

A2

A1

A0

0

0

0

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7

0

0

1

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

0

1

0

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

0

1

1

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

1

0

0

4-5-6-7-0-1-2-3

4-5-6-7-0-1-2-3

1

0

1

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

1

1

0

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

1

1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0

selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1

select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

FIGURE 3 – MODE REGISTER DEFINITION

M3 = 0

2

4

8

Reserved

Reserved

Reserved

M3 = 1

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

00

Valid

Valid

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Reserved

2

Reserved

Reserved

2.5

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Length

CAS Latency

BT

Mode Register (Mx)

Address Bus

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6-M0

M8

M7

Operating Mode

* M14 and M13

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

mode register).

0*

0*

Reserved

Reserved

Reserved

Reserved

M9

M10

M11

0

0

0

10

0

0

0

--

-

-

-

-

M12

0

0

-

14

13

12 11 10

9

8

7

6

5

4

3

2

1

0

PRECHARGE is nonpersistent in that it is either enabled

or disabled for each individual READ or WRITE command.

The device supports concurrent auto precharge if the

command to the other bank does not interrupt the data

transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is

initiated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

precharge command was issued at the earliest possible

another command to the same bank until the precharge

BURST TERMINATE

The BURST TERMINATE command is used to truncate

READ bursts (with auto precharge disabled). The most

recently registered READ command prior to the BURST

TERMINATE command will be truncated. The open page

which the READ burst was terminated from remains

open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the

DDR SDRAM and is analogous to CAS-BEFORE-RAS

(CBR) REFRESH in conventional DRAMs. This command

is nonpersistent, so it must be issued each time a refresh

is required. All banks must be idle before an AUTO

REFRESH command is issued.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”