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W3EG264M72AFSR262D3XG Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3EG264M72AFSR262D3XG Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
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6 / 13 page  W3EG264M72AFSRxxxD3 November 2004 Rev. 1 ADVANCED 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V. Includes PLL and register power Parameter Symbol Rank 1 Conditions DDR333@CL=2.5 Max DDR266:@CL=2, 2.5 Max DDR200@CL=2 Max Units Rank 2 Standby State Operating Current IDD0 One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 4995 4635 4635 mA IDD3N Operating Current IDD1 One device bank; Active-Read-Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 5805 5265 5265 mA IDD3N Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low) 144 144 144 rnA IDD2P Idle Standby Current IDD2F CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 2110 1930 1930 mA IDD2F Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE = (low) 1080 900 900 mA IDD3P Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 2470 2110 2110 mA IDD3N Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA. 5895 5085 5085 mA IDD3N Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 5625 4815 4815 rnA IDD3N Auto Refresh Current IDD5 tRC = tRC (MIN) 7370 6650 6650 mA IDD3N Self Refresh Current IDD6 CKE ≤ 0.2V 419 419 419 mA IDD6 Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 10125 8685 8685 mA IDD3N |
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