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W3EG2128M72AFSR262AD3XG Datasheet(PDF) 8 Page - White Electronic Designs Corporation

Part # W3EG2128M72AFSR262AD3XG
Description  2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

W3EG2128M72AFSR262AD3XG Datasheet(HTML) 8 Page - White Electronic Designs Corporation

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W3EG2128M72AFSR-D3
-AD3
8
White Electronic Designs
January 2006
Rev. 3
FINAL
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262
265
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
60
60
60
ns
AUTO REFRESH command period
tRFC
70
72
75
75
ns
21
ACTIVE to READ or WRITE delay
tRCD
15
15
15
15
ns
PRECHARGE command period
tRP
15
15
15
15
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
15
ns
DQS write preamble
tWPRE
0.25
0.25
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0000
ns
10,11
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write recovery time
tWR
15
15
15
15
ns
Internal WRITE to READ command delay
tWTR
2111
tCK
Data valid output window
NA
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
13
REFRESH to REFRESH command interval
tREFC
70.3
70.3
70.3
70.3
μs
12
Average periodic refresh interval
tREFI
7.8
7.8
7.8
7.8
μs
12
Terminating voltage delay to VCC
tVTD
0000
ns
Exit SELF REFRESH to non-READ command
tXSNR
70
75
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
200
200
tCK
Note:
• These parameters serve to support both SAMSUNG and MICRON components based modules.


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