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W3EG6433S265D3 Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3EG6433S265D3 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 12 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 November 2005 Rev. 2 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR333@CL=2.5 Max DDR266@CL=2 Max DDR266@CL=2/2.5 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 680 640 640 mA Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 880 800 800 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 24 24 24 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 200 180 180 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 240 200 200 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 360 320 320 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 1,120 960 960 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 1,160 1,000 1,000 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 1,320 1,240 1,240 mA Self Refresh Current IDD6 CKE ≤ 0.2V 16 16 16 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 2,400 2,000 2,000 mA NOTES: • Module IDD was calculated on the basis of component IDD and can be different measured according to dq hearing cap. • IDD specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. |
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