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W3EG6466S265AD4 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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W3EG6466S265AD4 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 13 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6466S-AD4 -BD4 January 2005 Rev. 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2 Parameter Symbol Conditions Max Max Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1600 1440 1360 mA Operating Current IDD1 One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. 1800 1640 1560 mA Precharge Power-Down Standby Current IDD2P All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) 48 48 48 mA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. 400 320 320 mA Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; tCK(MIN); CKE=(low) 560 480 480 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 880 720 720 mA Operating Current IDD4R Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. 2160 1840 1840 mA Operating Current IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. 2160 1800 1800 mA Auto Refresh Current IDD5 tRC=tRC(MIN) 2240 2000 2000 mA Self Refresh Current IDD6 CKE ≤ 0.2V 48 48 48 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 3120 2960 2720 mA * For DDR333 consult factory |
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