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W3EG7235S-JD3 Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3EG7235S-JD3 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 12 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7235S-JD3 PRELIMINARY November 2004 Rev. 2 IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM Components Only Parameter Rank 1 Conditions DDR266@CL = 2 Max DDR266@CL = 2.5 Max DDR200@CL = 2 Max Units Rank2 Stand By State Operating Current IDD0 One device bank; Active = Precharge; tRC = tRC(MIN); tCK = tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1890 1755 1755 mA IDD3N Operating Current IDD1 One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. 1980 1890 1890 mA IDD3N Precharge Power- Down Standby Current IDD2P All device banks idle; Power- down mode; tCK = tCK(MIN); CKE = (low) 54 54 54 mA IDD2P dle Standby Current IDD2F CS# = High; All device banks idle; tCK = tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 810 720 720 mA IDD2F Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; tCK(MIN); CKE = (low) 450 360 360 mA IDD3P Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active- Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 900 810 810 mA IDD3N Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA. 2070 1935 1935 mA IDD3N Operating Current IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. 2025 1890 1890 mA IDD3N Auto Refresh Current IDD5 tRC = tRC(MIN) 2880 2790 2790 mA IDD3N Self Refresh Current IDD6 CKE ≤ 0.2V 54 36 36 mA IDD6 Operating Current IDD7A Four bank interleaving Reads (BL = 4) with auto precharge with tRC = tRC (MIN); tCK = tCK(MIN); Address and control inputs change only during Active Read or Write commands. 3870 3735 3735 mA IDD3N |
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