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W3EG7263S263AJD3 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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W3EG7263S263AJD3 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
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5 / 13 page  5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7263S-D3 -JD3 -AJD3 April 2004 Rev. # 2 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C £ TA £ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V. Includes DDR SDRAM components and PLL and Register Parameter Symbol Rank 1 Conditions DDR333@CL=2.5 Max DDR266:@CL=2, 2.5 Max DDR200@CL=2 S Max Units Rank 2 Standby State Operating Current IDD0 One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. TBD 1715 1715 mA IDD3N Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. TBD 2255 2255 mA IDD3N Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low) TBD 54 54 rnA IDD2P Idle Standby Current IDD2F CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. TBD 671 671 mA IDD2F Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE = (low) TBD 540 540 mA IDD3P Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. TBD 1121 1121 mA IDD3N Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA. TBD 2795 2795 mA IDD3N Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. TBD 2795 2795 rnA IDD3N Auto Refresh Current IDD5 tRC = tRC (MIN) TBD 3281 3281 mA IDD3N Self Refresh Current IDD6 CKE £ 0.2V TBD 365 365 mA IDD6 Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. TBD 5315 5315 mA IDD3N |
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