W3EG72128S403D3 datasheet(5/12 Pages) WEDC

Part #	W3EG72128S403D3

Description	1GB - 2x64Mx72 DDR SDRAM UNBUFFERED

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

W3EG72128S-D3

-JD3

May 2005

Rev. 3

ADVANCED

White Electronic Designs

IDD SPECIFICATIONS AND TEST CONDITIONS

VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = 2.6V ± 0.1V

Includes DDR SDRAM component only

Parameter

Symbol Conditions

DDR400@

CL=3

Max

DDR333@

CL=2.5

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

DDR200@

CL=2

Max

Units

Operating Current

IDD0

One device bank; Active - Precharge;

tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM

and DQS inputs changing once per

clock cycle; Address and control

inputs changing once every two

cycles.

2475

2070

mA

Operating Current

IDD1

One device bank; Active-Read-

Precharge Burst = 2; tRC=tRC (MIN);

tCK=tCK (MIN); lOUT = 0mA; Address

and control inputs changing once per

clock cycle.

2745

2340

mA

Precharge Power-

Down Standby Current

IDD2P

All device banks idle; Power-down

mode; tCK=tCK (MIN); CKE=(low)

90

rnA

Idle Standby Current

IDD2F

CS# = High; All device banks idle;

tCK=tCK (MIN); CKE = high; Address

and other control inputs changing

once per clock cycle. VIN = VREF for

DQ, DQS and DM.

990

810

mA

Active Power-Down

Standby Current

IDD3P

One device bank active; Power-

Down mode; tCK (MIN); CKE=(low)

810

630

mA

Active Standby Current

IDD3N

CS# = High; CKE = High; One device

bank; Active-Precharge; tRC=tRAS

(MAX); tCK=tCK (MIN); DQ, DM and

DQS inputs changing twice per clock

cycle; Address and other control

inputs changing once per clock cycle.

1080

900

mA

Operating Current

IDD4R

Burst = 2; Reads; Continuous burst;

One device bank active; Address

and control inputs changing once

per clock cycle; TCK= TCK (MIN); lOUT

= 0mA.

2790

2385

mA

Operating Current

IDD4W

Burst = 2; Writes; Continuous burst;

One device bank active; Address

and control inputs changing once per

clock cycle; tCK=tCK (MIN); DQ,DM

and DQS inputs changing once per

clock cycle.

2835

2475

rnA

Auto Refresh Current

IDD5

tRC = tRC (MIN)

4185

3510

mA

Self Refresh Current

IDD6

CKE

≤ 0.2V

90

mA

Operating Current

IDD7A

Four bank interleaving Reads (BL=4)

with auto precharge with tRC=tRC

(MIN); tCK=tCK (MIN); Address and

control inputs change only during

Active Read or Write commands.

5130

4545

4500

mA

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