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W3HG128M64EEU665D4XXG Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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W3HG128M64EEU665D4XXG Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
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5 / 14 page  W3HG128M64EEU-D4 March 2006 Rev. 0 ADVANCED 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs DDR2 ICC SPECIFICATIONS AND CONDITIONS DDR2 SDRAM components only VCC = +1.8V ± 0.1V Parameter Symbol Condition 806 665 534 403 Units Operating one device bank active-precharge current; ICC0 tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 800 640 640 mA Operating one device bank active-read- precharge current; ICC1 IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. TBD 1,160 760 760 mA Precharge power-down current; ICC2P All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. TBD 56 40 40 mA Precharge quiet standby current; ICC2Q All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. TBD 480 328 280 mA Precharge standby current; ICC2N All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 520 360 280 mA Active power-down current; ICC3P All device banks open; tCK = tCK (ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Fast PDN Exit MR[12] = 0 TBD 320 240 200 mA Slow PDN Exit MR[12] = 1 TBD 80 80 80 mA Active standby current; ICC3N All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 560 400 320 mA Operating burst write current; ICC4W All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 1,440 1,040 960 mA Operating burst read current; ICC4R All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 1,640 1,160 1,080 mA Burst refresh current; ICC5 tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. TBD 2,160 2,000 1,920 mA Self refresh current; ICC6 CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. TBD 56 40 40 mA Operating device bank interleave read current; ICC7 All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC), AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING TBD 2,720 2,360 2,360 mA Note: • ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different. |
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