W3H32M64E-XSBX

ADVANCED*

1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

October 2005

Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package

FEATURES

Data rate = 667*, 533, 400

Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm

• 1.0mm pitch

DDR2 Data Rate = 667*, 533, 400

Supply Voltage = 1.8V ± 0.1V

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal

Four internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes

On Die Termination (ODT)

Adjustable data – output drive strength

Programmable CAS latency: 3, 4 or 5

Posted CAS additive latency: 0, 1, 2, 3 or 4

Write latency = Read latency - 1* tCK

Commercial, Industrial and Military Temperature

Ranges

Organized as 32M x 64, user configurable as 2 x

32M x 32

Weight: W3H32M64E-XSBX - 2.5 grams typical

BENEFITS

62% SPACE SAVINGS vs. FPBGA

Reduced part count

42% I/O reduction vs FPBGA

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Upgradeable to 64M x 64 density (contact factory

for information)

* This product is under development, is not qualified or characterized and is subject

to change or cancellation without notice.

Area

62%

4 x 90 balls = 360 balls

208 Balls

42%

S

A

V

I

N

G

S

I/O

Count

Actual Size

W3H32M64E-XSBX

CSP Approach (mm)

90

FBGA

11.0

19.0

20

16

90

FBGA

11.0

90

FBGA

11.0

90

FBGA

11.0

FIGURE 1 – DENSITY COMPARISONS