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LP3879SD-1.0 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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LP3879SD-1.0 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 11 page Electrical Characteristics (Continued) Limits in standard typeface are for T J = 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C. Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Unless otherwise specified: V IN = 3.0V, VOUT = 1V, IL = 1 mA, COUT = 10 µF, CIN = 4.7 µF, VS/D = 2V, C BYPASS =10nF. Symbol Parameter Conditions Min (Note 6) Typical (Note 7) Max (Note 6) Units SHUTDOWN INPUT V S/D S/D Input Voltage V H = Output ON 1.4 1.6 V V L = Output OFF I IN ≤ 10 µA 0.1 0.50 V OUT ≤ 10 mV I IN ≤ 50 µA 0.6 I S/D S/D Input Current V S/D = 0 0.02 −1 µA V S/D =5V 5 15 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 k Ω resistor. Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: The value of θJ−A for the LLP (SD) and PSOP (MRA) packages are specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. If a four layer board is used with maximum vias from the IC center to the heat dissipating copper layers, values of θJ−A which can be obtained are approximately 60˚C/W for the PSOP-8 and 40˚C/W for the LLP-8 package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to ground. Note 5: The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output above the input will turn on this diode and may induce a latch-up mode which can damage the part (see Application Hints). Note 6: Limits are guaranteed through testing, statistical correlation, or design. Note 7: Typical numbers reperesent the most likely norm for 25˚C operation. www.national.com 4 |
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