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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WE32K32-XXX

March 2006

Rev. 4

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

AC Write Characteristics

WRITE CYCLE

Write Cycle Parameter

Symbol

-80

-90

-120

-150

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Write Cycle Time, TYP = 6ms

10

10

10

10

ms

Address Set-up Time

0

0

30

30

ns

Write Pulse Width (WE# or CS#)

100

100

150

150

ns

Chip Select Set-up Time

0000

ns

Address Hold Time

50

50

100

100

ns

Data Hold Time

0

0

10

10

ns

Chip Select Hold Time

0000

ns

Data Set-up Time

50

50

100

100

ns

Write Pulse Width High

50

50

50

50

ns

Output Enable Set-up Time

10

10

10

10

ns

Output Enable Hold Time

10

10

10

10

ns

WRITE

A write cycle is initiated when OE# is high and a low pulse

is on WE# or CS# with CS# or WE# low. The address

is latched on the falling edge of CS# or WE# whichever

occurs last. The data is latched by the rising edge of CS#

or WE#, whichever occurs first. A byte write operation will

automatically continue to completion.

WRITE CYCLE TIMING

Figures 4 and 5 show the write cycle timing relationships.

A write cycle begins with address application, write enable

and chip select. Chip select is accomplished by placing

the CS# line low. Write enable consists of setting the WE#

line low. The write cycle begins when the last of either CS#

or WE# goes low.

The WE# line transition from high to low also initiates

an internal 150 µsec delay timer to permit page mode

operation. Each subsequent WE# transition from high to

low that occurs before the completion of the 150 µsec time

out will restart the timer from zero. The operation of the

timer is the same as a retriggerable one-shot.