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WED2ZL361MV38BI Datasheet(PDF) 3 Page - White Electronic Designs Corporation |
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WED2ZL361MV38BI Datasheet(HTML) 3 Page - White Electronic Designs Corporation |
3 / 12 page 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2ZL361MV June 2004 Rev. 3 TRUTH TABLES Synchronous Truth Table CEx# ADV# WE# BWx# OE# CKE# CLK Address Accessed Operation H L XXX L ↑ N/A Deselect X H XXX L ↑ N/A Continue Deselect LL H X LL ↑ External Address Begin Burst Read Cycle XHX X L L ↑ Next Address Continue Burst Read Cycle L L HXH L ↑ External Address NOP/Dummy Read XHX XH L ↑ Next Address Dummy Read LLLL X L ↑ External Address Begin Burst Write Cycle XHX L X L ↑ Next Address Continue Burst Write Cycle LLL H X L ↑ N/A NOP/Write Abort XHXHX L ↑ Next Address Write Abort XXXXX H ↑ Current Address Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( ↑ ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE#). 6. CEx# refers to the combination of CE1#, CE2# and CE2#. Write Truth Table WE# BWa# BWb# BWc# BWd# Operation H XXXX Read L L H H H Write Byte a L H L H H Write Byte b L H H L H Write Byte c L H H H L Write Byte d LLLLL Write All Bytes L HHHH Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CLK ( ↑ ). |
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