WED3C755E8M-XBX

11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

May, 2003

Rev 2

FIG. 6 - POWER SUPPLY FILTER CIRCUIT

PLL POWER SUPPLY FILTERING

the WED3C755E8M-XBX to provide power to the clock

generation phase-locked loop and L2 cache delay-locked

loop respectively. To ensure stability of the internal clock,

filtered of any noise in the 500kHz to 10 MHz resonant

frequency range of the PLL. A circuit similar to the

one shown in Figure 6 using surface mount capacitors

with minimum Effective Series Inductance (ESL) is

recommended. Multiple small capacitors of equal value

are recommended over a single large value capacitor.

The circuit should be placed as close as possible to the

An identical but separate circuit should be placed as close

periphery of the 255 BGA footprint, without the inductance

is proportionately less critical.

PULL-UP RESISTOR REQUIREMENTS

The WED3C755E8M-XBX requires pull-up resistors (1

kW-5 kW) on several control pins of the bus interface to

maintain the control signals in the negated state after they

have been actively negated and released by the processor

or other bus masters. These pins are TS#, ABB#, AACK#,

ARTRY#, DBB#, DBWO#, TA#, TEA#, and DBDIS#.

DRTRY# should also be connected to a pull-up resistor

(1 kW-5 kW) if it will be used by the system; otherwise,

this signal should be connected to HRESET# to select

NO-DRTRY mode.

Three test pins also require pull-up resistors (100 W-1 kW).

These pins are L1_TSTCLK, L2_TSTCLK, and LSSD_

MODE#. These signals are for factory use only and must

In addition, CKSTP_OUT# is an open-drain style output

that requires a pull-up resistor (1 kW-5 kW) if it is used by

the system. During inactive periods on the bus, the address

and transfer attributes may not be driven by any master

and may, therefore, float in the high-impedance state for

relatively long periods of time. Since the processor must

continually monitor these signals for snooping, this float

condition may cause additional power draw by the input

receivers on the processor or by other receivers in the

system. These signals can be pulled up through weak (10

kW) pull-up resistors by the system or may be otherwise

driven by the system during inactive periods of the bus to

avoid this additional power draw, but address bus pull-up

resistors are not neccessary for proper device operation.

The snooped address and transfer attribute inputs are:

A[0:31], AP[0:3], TT[0:4], TBST#, and GBL#.

The data bus input receivers are normally turned off

when no read operation is in progress and, therefore, do

not require pull-up resistors on the bus. Other data bus

receivers in the system, however, may require pull-ups, or

that those signals be otherwise driven by the system during

inactive periods by the system. The data bus signals are:

DH[0:31], DL[0:31], and DP[0:7].

If 32-bit data bus mode is selected, the input receivers of

the unused data and parity bits will be disabled, and their

outputs will drive logic zeros when they would otherwise

normally be driven. For this mode, these pins do not require

pull-up resistors, and should be left unconnected by the

system to minimize possible output switching.

If address or data parity is not used by the system, and

the respective parity checking is disabled through HID0,

the input receivers for those pins are disabled, and those

pins do not require pull-up resistors and should be left

unconnected by the system. If all parity generation is

disabled through HID0, then all parity checking should

also be disabled through HID0, and all parity pins may be

left unconnected by the system.

2.2

µF

2.2

µF

GND

Low ESL surface mount capacitors

10

Ω