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74HCT03N Datasheet(PDF) 2 Page - NXP Semiconductors |
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74HCT03N Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 8 page December 1990 2 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC/HCT03 FEATURES • Level shift capability • Output capability: standard (open drain) • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT03 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT03 provide the 2-input NAND function. The 74HC/HCT03 have open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2× fi + ∑ (CL × VCC2 × fo) + ∑ (VO2/RL) × duty factor LOW, where: fi = input frequency in MHz fo = output frequency in MHz VO = output voltage in V CL = output load capacitance in pF VCC = supply voltage in V RL = pull-up resistor in MΩ ∑ (CL × VCC2 × fo) = sum of outputs ∑ (VO2/RL) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 3. The given value of CPD is obtained with: CL = 0 pF and RL = ∞ ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPZL/ tPLZ propagation delay CL = 15 pF; RL =1 kΩ; VCC = 5 V 8 10 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per gate notes 1, 2 and 3 4.0 4.0 pF |
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