WE512K8, WE256K8,

WE128K8-XCX

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

May 2000

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Figure 5 shows Read cycle waveforms. A read cycle begins

with selection address, chip select and output enable. Chip

select is accomplished by placing the CS# line low. Output

enable is done by placing the OE# line low. The memory

places the selected data byte on I/O0 through I/O7 after the

access time. The output of the memory is placed in a high

impedance state shortly after either the OE# line or CS# line

is returned to a high level.

AC READ CHARACTERISTICS (See Figure 5)

FOR WE512K8-XCX

Parameter

Symbol

-150

-200

-250

-300

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Read Cycle Time

trc

150

200

250

300

ns

Address Access Time

tacc

150

200

250

300

ns

Chip Select Access Time

tacs

150

200

250

300

ns

Output Hold from Address Change, OE# or CS#

toh

0000

ns

Output Enable to Output Valid

toe

85

85

100

125

ns

Chip Select or Output Enable to High Z Output

tdf

70

70

70

70

ns

FOR WE256K8-XCX and WE128K8-XCX

Parameter

Symbol

-150

-200

Unit

Min

Max

Min

Max

Read Cycle Time

trc

150

200

ns

Address Access Time

tacc

150

200

ns

Chip Select Access Time

tacs

150

200

ns

Output Hold from Address Change, OE# or CS#

toh

0

0

ns

Output Enable to Output Valid

toe

85

85

ns

Chip Select or Output Enable to High Z Output

tdf

70

70

ns

FIGURE 5 – READ WAVEFORMS

ADDRESS

CS#

OE#

OUTPUT

NOTE:

READ