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WE512K8-250CQA Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WE512K8-250CQA Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 13 page WE512K8, WE256K8, WE128K8-XCX 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2000 Rev. 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. WRITE CYCLE TIMING Figures 6 and 7 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE line low. The write cycle begins when the last of either CS# or WE# goes low. The WE# line transition from high to low also initiates an internal 150µsec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150µsec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot. WRITE Write operations are initiated when both CS# and WE# are low and OE# is high. The EEPROM devices support both a CS# and WE# controlled write cycle. The address is latched by the falling edge of either CS# or WE#, whichever occurs last. The data is latched internally by the rising edge of either CS# or WE#, whichever occurs first. A byte write operation will automatically continue to completion. AC WRITE CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol 512K x 8 256K x 8 128K x 8 Unit Min Max Min Max Min Max Write Cycle Time, TYP = 6mS tWC 10 10 10 ms Address Set-up Time tAS 10 30 30 ns Write Pulse Width (WE# or CS#) tWP 150 150 150 ns Chip Select Set-up Time tCS 000 ns Address Hold Time (1) tAH 125 50 50 ns Data Hold Time tDH 10 0 0 ns Chip Select Hold Time tCH 000 ns Data Set-up Time tDS 100 100 100 ns Output Enable Set-up Time tOES 10 30 30 ns Output Enable Hold Time tOEH 10 0 0 ns Write Pulse Width High tWPH 50 50 50 ns NOTES: 1. A17 and A18 must remain valid through WE# and CS# low pulse, for 512K x 8. A15, A16, and A17 must remain valid through WE# and CS# low pulse, for 256K x 8. A15 and A16 must remain valid through WE# and CS# low pulse, for 128K x 8. |
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