WED3EG72M18S403JD3ISG datasheet(6/12 Pages) WEDC

Part #	WED3EG72M18S403JD3ISG

Description	128MB - 16Mx72 DDR SDRAM UNBUFFERED

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED3EG7218S-JD3

June 2006

Rev. 2

PRELIMINARY

IDD1 : OPERATING CURRENT : ONE BANK

1.

Typical Case : VCC=2.5V, T=25°C

2.

Worst Case : VCC=2.7V, T=10°C

3.

Only one bank is accessed with tRC (min), Burst

Mode, Address and Control inputs on NOP edge

are changing once per clock cycle. IOUT = 0mA

4.

Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRCD=2*tCK, tRAS=5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the

same timing with random address changing;

50% of data changing at every burst

•

DDR266 (133MHz, CL=2.5) : tCK=7.5ns,

CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

changing; 50% of data changing at every burst

•

DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,

BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

changing; 50% of data changing at every burst

•

DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,

tRCD=10*tCK, tRAS=7*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

changing; 50% of data changing at every burst

•

DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,

tRCD=15*tCK, tRAS=7*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat

the same timing with random address

changing; 50% of data changing at every burst

IDD7A : OPERATING CURRENT : FOUR BANKS

1.

Typical Case : VCC=2.5V, T=25°C

2.

Worst Case : VCC=2.7V, T=10°C

3.

Four banks are being interleaved with tRC (min),

Burst Mode, Address and Control inputs on NOP

edge are not changing. Iout=0mA

4.

Timing Patterns :

•

DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,

BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with

Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0

repeat the same timing with random address

changing; 100% of data changing at every

burst

•

DDR266 (133MHz, CL=2.5) : tCK=7.5ns,

CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK

Read with Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

•

DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,

BL=4, tRRD=2*tCK, tRCD=2*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

•

DDR333 (166MHz, CL=2.5) : tCK=6ns,

BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with

Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

•

DDR400 (200MHz, CL=3) : tCK=5ns,

BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with

Autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N

A1 R0 - repeat the same timing with random

address changing; 100% of data changing at

every burst

DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A

Legend:

A = Activate, R = Read, W = Write, P = Precharge, N = NOP

A (0-3) = Activate Bank 0-3

R (0-3) = Read Bank 0-3

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