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WED3EG72M32S202JD3SG Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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WED3EG72M32S202JD3SG Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 12 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7232S-JD3 June 2006 Rev. 6 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR400@ CL=3 Max DDR333@ CL=2.5 Max DDR266@ CL=2 Max DDR266@ CL=2.5 Max DDR200@ CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1215 1125 1125 1125 1125 mA Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 1530 1530 1530 1530 1530 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 36 36 36 36 36 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 540 450 450 450 450 mA Active Power-Down Standby Current IDD3P One device bank active; Power- Down mode; tCK (MIN); CKE=(low) 360 270 270 270 270 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 630 540 540 540 540 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 1800 1575 1575 1575 1575 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 1755 1575 1575 1575 1575 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 2340 2295 2295 2295 2295 mA Self Refresh Current IDD6 CKE ≤ 0.2V 36 36 36 36 36 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4230 3690 3690 3690 3690 mA |
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