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74HC109N Datasheet(PDF) 2 Page - NXP Semiconductors |
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74HC109N Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 9 page 1997 Nov 25 2 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 FEATURES • J, K inputs for easy D-type flip-flop • Toggle flip-flop or “do nothing” mode • Output capability: standard • ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V nCP to nQ, nQ15 17 ns nSD to nQ, nQ12 14 ns nRD to nQ, nQ12 15 ns fmax maximum clock frequency 75 61 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop notes 1 and 2 20 22 pF |
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