WED416S8030A-SI

2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

October 2004

Rev. 4

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Symbol

Type

Signal

Polarity

Function

CK

Input

Pulse

Positive Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

CKE

Input

Level

Active High

Activates the CK signal when high and deactivates the CK signal when low. By deactivating

the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.

CE#

Input

Pulse

Active Low

CE# disable or enable device operation by masking or enabling all inputs except CK, CKE

and DQM.

RAS#,

CAS#, WE#

Input

Pulse

Active Low

When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the

operation to be WE executed by the SDRAM.

BA0, BA1

Input

Level

-

Selects which SDRAM bank is to be active.

A0-11,

A10/AP

Input

Level

-

During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when

sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke

Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,

autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low,

autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction

with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be

precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to

define which bank to precharge.

DQ0-15

Input/Output

Level

-

Data Input/Output are multiplexed on the same pins.

L(U)DQM

Input

Pulse

Mask Active High

The Data Input/Output mask places the DQ buffers in a high impedance state when sampled

high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers

like an output enable. In Write mode, DQM has a latency of zero and operates as a word

mask by allowing input data to be written if it is low but blocks the Write operation if DQM is

high.

Supply

Power and ground for the input buffers and the core logic.

Supply

Isolated power and ground for the output buffers to improve noise immunity.

INPUT/OUTPUT FUNCTIONAL DESCRIPTION